Piper Companies is currently seeking a Senior Director RTL Design to work on-site in Saratoga, CA 5 days per week. The ideal Senior Director RTL Design is eager to join a cutting-edge startup and lead the development of Networking IC from definition, specification, architecture, execution and bring to market of Networking devices.

Responsibilities of the Senior Director RTL Design:

Lead and guide the Chip RTL team technically.
Work with Chip and System Architects to convert architecture requirements into microarchitecture and design.
Perform RTL coding in Verilog and/or VLSI, review code, and debug.
Use expertise in Ethernet protocols to guide design decisions.
Establish and maintain quality standards for RTL development.
Participate in post-silicon activities like bring-up, platform validation, characterization, parameter optimization, and final productization.
Collaborate with customers and stakeholders to understand feature needs and create implementable specifications.

Qualifications of the Senior Director RTL Design:

15+ years' experience in hardware digital design with domain expertise in the networking industry
Strong experience leading teams technically in a Director level position
Hands on expertise in optimizing hardware for overall product performance and efficiency.
Strong experience with micro-architectural specification of ASICs.
Good understanding of the ASIC design flow, including DFT and physical implementation requirements.
Must be eligible to work in the United States and obtain and maintain an Active U.S. Government Secret Clearance

Compensation for the Senior Director RTL Design

Salary Range: $260,00- - $350,000 annually
Comprehensive Benefits: Medical, Dental, Vision, 401K, PTO, Sick Leave as required by law, and Holidays

This job opens for applications on 3/12/2025. Applications for this job will be accepted for at least 30 days from the posting date.

Keywords: Senior Director, Director, RTL Design, Chip RTL, microarchitecture, RTL coding, hardware digital design, ASIC micro-architecture, digital system layout, ASIC design flow, Verilog, VLSI

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